From silicon masks to Kubernetes clusters, this dual-track BS immerses students in RTL design with SystemVerilog, GPU kernel optimization via CUDA, and full-stack microservices hardened by DevSecOps CI/CD (DS-CD). Labs fabricate RISC-V SoCs in the USC nanofab, while capstones deploy edge AI on Jetson boards for smart-city sensor grids. Coursework in quantum algorithms and zero-knowledge proofs future-proofs graduates against tech obsolescence.
FPGA-based CNN accelerator for real-time traffic detection
Zero-trust bootloader with hardware root-of-trust (HWRoT)
Containerized IoT gateway running eBPF telemetry
Dynamic voltage scaling controller using RL on SoC
Post-quantum lattice crypto engine in ASIC flow
DPU offload plugin benchmarking RDMA vs. TCP
Open-source RISC-V laptop prototype (RV-Book)
Chaos-engineering suite injecting faults in mesh networks
3-D IC thermal simulation comparing TSV layouts
Automated RTL linting with GPT-based code-review bot
Quantum circuit transpiler optimizing CX gate depth
Edge AI vision kit classifying recycling streams
Memory-safe Rust driver for NVMe SSDs
Policy paper on right-to-repair for embedded devices
AR debugger overlaying logic analyzer waveforms
Design hardware and code that power the digital future.
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